The present invention relates to MOSFET devices, and more specifically, the formation of an ultra low-k film between the gate and source/drain contacts reduces the gate-source and gate-drain parasitic capacitances.
FIG. 1 shows exemplarily a finFET (Fin Field Effect Transistor) 100, a type of non-planar transistor used in many modern processor designs. It can be fabricated on an SOI (silicon on insulator) substrate or on a Si (silicon) substrate and is characterized by one or more fin structures 102 that form the conductive channel controlled by the gate structure 104. This fin-shaped structure permits multiple gates to operate on a single transistor, such as demonstrated by structure 110, and permits devices that are smaller, faster, and more energy efficient.
The present inventors have recognized that the shrinking of the finFET structure results in an undesired relatively high parasitic capacitance between the gate and source/drain contacts and have identified various factors in the conventional fabrication of finFET devices that contribute to this high parasitic capacitance, as follows. First, the shrinking of the gate pitch limits the spacer thickness, and a thinner spacer provides a capacitor structure with higher capacitance. Additionally, an etchant that is selective to the material used for the spacer limits the options for the spacer material. Finally, the spacer is often damaged during the contact open stage of fabrication, which is the fabrication stage during which the source and drain regions are exposed for metal deposition for contacts.
The present invention discloses a novel flow and unique structure to resolve the above-identified issues. Although the following discussion uses the finFET for purpose of explanation, the present invention is not intended as limited specifically to finFET structures since it is equally applicable to any MOSFET-like structure having a gate structure with spacers to separate the gate from the source/drain structures.